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M62421SP/FP Tone and Volume Controller with 2 Line Control REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Outline M62421SP/FP is the tone and volume controller with 2 line control. This IC can apply the broad application because of low noise and distortion. Feature * Tone (Bass/Treble) control and 1 dB step volume control are enabled. * Low noise and low distortion. VNO = 4.5 Vrms, THD = 0.1% max * Controlling by 2 Line serial data. Application * Mini-Stereo, etc Recommended Operating Condition Supply voltage range: 5.5 ~ 9.5 V (analog), 4.5 ~ 5.5 V (digital) Rated supply voltage: 9 V (analog), 5 V (digital) System Block Diagram Lch IN VOLUME BASS TREBLE Lch OUT TONE CONTROL Rch IN VOLUME D A T C L K BASS TREBLE Rch OUT TONE CONTROL MPU REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 1 of 13 M62421SP/FP Block Diagram SIMOUT2 SIMIN2 CH2 IN BASS2 AGND DVDD AVDD OUT2 TRE2 20 19 18 + - 17 16 15 14 13 12 11 420 1.8 k VR3 SIMAMP2 1.8 k VR5 420 200 k 200 k 117 k ref S2 S4 S6 S8 TONE AMP2 6.4 k VR2 ref + - VOLAMP2 + - 6.4 k ref VR1 VOLAMP1 CONTROL LOGIC 6.4 k + - 6.4 k TONE AMP1 ref ref S1 S3 S5 S7 200 k 200 k VR5 1.8 k 420 117 k SIMAMP1 VR3 1.8 k + - 420 1 REF 2 CH1 IN 3 SIMIN1 4 SIMOUT1 5 BASS1 6 TRE1 7 OUT1 8 DGND 9 DAT 10 CLK REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 2 of 13 CS + - M62421SP/FP Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name REF CH1 IN SIMIN1 SIMOUT1 BASS1 TRE1 OUT1 DGND DAT CLK CS DVDD AGND OUT2 TRE2 BASS2 SIMOUT2 SIMIN2 CH2 IN AVDD I/O I I I O I I O -- I I I -- -- O I I O I I -- Description Reference voltage terminal for analog Input terminal (ch1) Pin for capacitor of simulated inductor 1 Pin for capacitor of simulated inductor 1 Pin for capacitor of ch1-side bass setting Pin for capacitor of ch1-side treble setting Output terminal (ch1) Digital GND I/O terminal of DATA 2 line bus format Input terminal of CLOCK 2 line bus format Chip select terminal VDD for digital circuit GND for analog circuit Output terminal (ch2) Pin for capacitor of ch2-side treble setting Pin for capacitor of ch2-side bass setting Pin for capacitor of simulated inductor 2 Pin for capacitor of simulated inductor 2 Input terminal (ch2) VCC for analog circuit REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 3 of 13 M62421SP/FP Absolute Maximum Ratings Item Analog supply voltage Digital supply voltage Power dissipation Thermal derating ratio Operating temperature Storage temperature Symbol AVdd DVdd Pd K Topr Tstg Limits 10.0 7.0 750 (SP) 550 (FP) 7.5 (SP) 5.5 (FP) -20 ~ +75 -40 ~ +125 Unit V V mW mW/C C C Condition Ta 25C Ta > 25C Thermal Derating Power dissipation Pd (mW) 1200 1000 800 600 400 200 0 0 25 50 75 FP 375 mW 275 mW SP 750 mW 550 mW 100 125 150 Ambient Temperature Ta (C) Recommended Operating Condition (Ta = 25C unless otherwise noted) Item Analog supply voltage Digital supply voltage H level input voltage (logic circuit) L level input voltage (logic circuit) Symbol AVDD DVDD VIH VIL Min 5.5 4.5 0.7 DVDD 0 Typ 9.0 5.0 -- -- Max 9.5 5.5 VDD 0.3 DVDD Unit V V V V REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 4 of 13 M62421SP/FP Electric Characteristics (Ta = 25C, AVdd = 9 V, DVdd = 5 V and bass and treble = 0 dB unless otherwise noted) (1) Supply Voltage Item Analog supply current Symbol Icc Min -- Limit Typ 10 Max 20 Unit mA Condition Digital supply current Idd -- 0 2 A * * * * * * AVdd = 9.0 V measure terminal = 20 pin no signal input DVdd = 5 V measure terminal = 12 pin no signal input (2) I/O Characteristics Item Maximum input voltage Symbol VIM Min 2.0 Limit Typ 3.2 Max -- Unit Vrms Condition 2, 19 pin input 7, 14 pin output RL = 10 k, THD = 1%, f = 1 kHz ATT = -6 dB 7 pin, 14 pin, no signal Vin = 0 dBm, FLAT, f = 1 kHz 2 ~ 7 pin, 19 ~ 14 pin gain IHF-A filter no signal Rg = 10 k 7, 14 pin 7 pin, 14 pin f = 1 kHz Vo = 0.5 Vrms, RL = 10 k LPF = 30 kHz RL = 10 k S: Vin = 1 Vrms, f = 1 kHz M: Rg = 10 k, IHF-A filter Output voltage Gain Output noise voltage Vodc Gv Vono 4.35 -2 -- 4.5 0 4.5 4.65 2 10 V dB Vrms Total harmonic distortion THD -- 0.007 0.1 % Channel separation CT -- -100 -70 dB (3) Tone Characteristics Item Tone control gain (bass) Tone control gain (treble) Symbol Gbassb Gbassc Gtrebb Gtrebc Min 9 -15 9 -15 Limit Typ 12 -12 12 -12 Max 15 -9 15 -9 Unit dB dB dB dB f = 100 Hz f = 10 kHz Condition (4) Volume Characteristics Item Maximum attenuation Minimum attenuation Symbol ATTmax ATTmin Min -108 -1.5 Limit Typ -100 0 Max -80 1.5 Unit dB dB Condition f = 1 kHz, Vin = 0 dBm 2 pin ~ 7 pin 19 pin ~ 14 pin gain IHF-A-filter REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 5 of 13 M62421SP/FP Function Explanation Equivalent Circuit of Tone Control The resonance circuit is able to construct by using built-in amplifier for simulated inductor. (Shows the constant as follow) Inside IC R3 C1 C2 R1 ( = 1.8 k) - + SIMAMP R2 ( = 117 k) ref Figure 1 The circuit used simulated inductor Center frequency: f0 = 1 / 2 Q= C1 * C2 * R1 * R2 [Hz] (C2 * R2) / (C1 * R1) Example: BASS band (f 100 Hz) R1 = 1.8 k, R2 =117 k C1 = 0.47 , C2 = 0.022 ref L C1 R3 Figure 2 The equivalent circuit used L Figure1 is equal to figure2. The following relation is concluded. L = C2 * ER1 * ER2 REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 6 of 13 M62421SP/FP Input Data Format Input direction D0 0/1 D1 0/1 D2 D3 D4 D5 VOLUME D6 D7 D8 D9 0/1 D10 0 D11 0 0/1 TREBLE BASS 1 1 1 0 D12 0: BOTH 1: ONLY 1CHANNEL These functions are effective only VOLUME data 0: 1ch 1: 2ch 0: MUTE OFF 1: MUTE ON DATA SELECT 0: VOLUME/MUTE 1: BASS/TREBLE If CS pin (11 pin) is "L" 0, and if "H" 1. REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 7 of 13 M62421SP/FP Volume Control Volume Code ATT 0 dB -4 dB -8 dB -12 dB -16 dB -20 dB -24 dB -28 dB -32 dB -36 dB -40 dB -44 dB -48 dB -52 dB -56 dB -60 dB -64 dB -68 dB -72 dB -76 dB -80 dB - dB D2 H L H L H L H L H L H L H L H L H L H L H L D3 L L H H L L H H L L H H L L H H L L H H L L D4 H H L L L L H H H H L L L L H H H H L L L L D5 L L L L L L H H H H H H H H L L L L L L L L D6 H H H H H H L L L L L L L L L L L L L L L L ATT 0 dB -1 dB -2 dB -3 dB D7 H L H L D8 H H L L Tone Level Control Tone Code Bass 12 dB 10 dB 8 dB 6 dB 4 dB 2 dB 0 dB -2 dB -4 dB -6 dB -8 dB -10 dB -12 dB Note: D7 L L L L L L L H H H H H H D6 H H H L L L L L L L H H H D5 H L L H H L L L H H L L H D4 L H L H L H L H L H L H L D3 L L L L L L L H H H H H H D2 H H H L L L L L L L H H H Treble D1 H L L H H L L L H H L L H D0 L H L H L H L H L H L H L Not used "HHHH", "LHHH", "HLLL" Mute Control On condition D9 = 1, MUTE can be set up. In MUTE, VOLUME LEVEL is set up VOL = - automatically. REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 8 of 13 M62421SP/FP Data and Clock CLK D0 DAT Latch signal "H" Latch signal is read by CLK fall edge. D1 D2 D3 D10 D11 D12 DATA is read by CLK rise edge. Bus Line Timing Specification tcr 75% 25% tr tWHC tf tWLC tSD tHD Item CLK clock frequency The HIGH period of the clock The LOW period of the clock Rise time of CLK line Fall time of CLK line Set-up time DATA Hold time DATA Symbol tcr tWHC tWLC tr tf tSD tHD Min 4 1.6 1.6 -- -- 0.8 0.8 Max -- -- -- 0.4 0.4 -- -- Units s s s s s s s REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 9 of 13 M62421SP/FP Level Diagram INPUT TERMINAL CH1 IN G1 - + VOLAMP1 ref G1 TONEAMP1 6.4 k 6.4 k - + OUTPUT TERMINAL CH1 OUT -12 dB ~ +12 dB G2 0 dB ~ - dB 117 k ref - + 1.8 k INPUT TERMINAL CH2 IN Same to CH1 OUTPUT TERMINAL CH2 OUT REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 10 of 13 M62421SP/FP Logic Circuit Analog block - + ref TONE AMP1 VOLAMP1 + - Level shifter Level shifter Decoder,Iatch for volume control Decoder,Iatch for tone control CS Timing generator DAT Shift register CLK REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 11 of 13 M62421SP/FP Application Example OUT2 ref 0.033 F 0.022 F 0.47 F 2.2 F DVDD 2.2 F IN2 VCC 20 AGND DVDD or GND 19 18 + - 17 16 15 14 13 12 11 420 1.8 k VR3 SIMAMP2 1.8 k VR5 420 200 k 200 k TONE AMP2 117 k ref S2 S4 S6 S8 VR2 6.4 k + - + - 6.4 k ref VOLAMP2 VOLAMP1 + - CONTROL LOGIC ref VR1 6.4 k + - TONE AMP1 6.4 k ref ref S1 S3 S5 S7 200 k 200 k VR5 1.8 k 420 117 k SIMAMP1 VR3 1.8 k 420 + - Reference circuit example 470 F 4.7 k 4.7 k 1 2 3 4 5 6 7 8 9 10 0.022 F Reference voltage 2.2 F 0.47 F 0.033 F ref MPU OUT1 DGND 2.2 F IN1 REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 12 of 13 M62421SP/FP Package Dimensions JEITA Package Code P-SDIP20-6.3x19-1.78 RENESAS Code PRDP0020BA-A Previous Code 20P4B MASS[Typ.] 1.0g 20 11 1 10 c *1 e1 E *2 D NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. A A2 Reference Dimension in Millimeters Symbol e SEATING PLANE *3 b 3 bp e1 D E A A1 A2 bp b3 c e L Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 0 15 1.528 1.778 2.028 3.0 JEITA Package Code P-SOP20-5.3x12.6-1.27 L RENESAS Code PRSP0020DA-A Previous Code 20P2N-A MASS[Typ.] 0.3g 20 11 HE *1 E A1 F 1 Index mark 10 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. c *2 D A2 A1 Reference Dimension in Millimeters Symbol *3 e bp y Detail F D E A2 A1 A bp c HE e y L Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 A REJ03F0208-0201 Rev.2.01 Mar 31, 2008 Page 13 of 13 L Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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